Barretenberg
The ZK-SNARK library at the core of Aztec
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gate_data.hpp
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1// === AUDIT STATUS ===
2// internal: { status: Complete, auditors: [Luke], commit: }
3// external_1: { status: not started, auditors: [], commit: }
4// external_2: { status: not started, auditors: [], commit: }
5// =====================
6
7#pragma once
9#include <cstdint>
10
11namespace bb {
12
13// 3-wire addition gate: a*a_scaling + b*b_scaling + c*c_scaling + const_scaling = 0
14template <typename FF> struct add_triple_ {
15 uint32_t a;
16 uint32_t b;
17 uint32_t c;
22};
23
24// 4-wire addition gate: a*a_scaling + b*b_scaling + c*c_scaling + d*d_scaling + const_scaling = 0
25template <typename FF> struct add_quad_ {
26 uint32_t a;
27 uint32_t b;
28 uint32_t c;
29 uint32_t d;
35};
36
37// 4-wire mul-add gate: a*b*mul_scaling + a*a_scaling + b*b_scaling + c*c_scaling + d*d_scaling + const_scaling = 0
38template <typename FF> struct mul_quad_ {
39 uint32_t a;
40 uint32_t b;
41 uint32_t c;
42 uint32_t d;
49};
50
51// Bilinear / batched-eq gate (Mega flavors only; see relations/bilinear_or_batched_eq_check_relation.hpp).
52// Two row-modes, each populating a different set of wires + selectors:
53// - Bilinear: enforces q_m·a·b + q_5·a·c + q_l·a + q_r·b + q_o·c + q_4·d + q_c = 0.
54// Wires are (a, b, c, d): two products sharing wire a, on the pairs (a, b) and (a, c), a
55// linear term on each wire, and a constant. Wire d appears only in its linear term.
56// - BatchedEq: enforces q_l·a + q_r·b + q_c = 0 (batched-eq-half-1)
57// and q_o·c + q_4·d + q_m = 0 (batched-eq-half-2).
58enum class BilinearBatchedEqMode : uint8_t { Bilinear, BatchedEq };
59
60template <typename FF> struct bilinear_batched_eq_gate_ {
62 uint32_t a;
63 uint32_t b;
64 uint32_t c;
65 uint32_t d;
70 FF q_c; // batched-eq-half-1 constant in BatchedEq mode
71 FF q_m; // first product (a·b) selector in Bilinear mode; batched-eq-half-2 constant in BatchedEq mode
72 FF q_5; // second product (a·c) selector in Bilinear mode; unused (0) in BatchedEq mode
73};
74
75// Arithmetic gate with standard selector naming: q_m*a*b + q_l*a + q_r*b + q_o*c + q_c = 0
76template <typename FF> struct arithmetic_triple_ {
77 uint32_t a;
78 uint32_t b;
79 uint32_t c;
85
86 friend bool operator==(arithmetic_triple_<FF> const& lhs, arithmetic_triple_<FF> const& rhs) = default;
87};
88
90
91// Goblin ECCVM operation: stores op type, point coordinates (split into limbs), and scalar
93 uint32_t op;
94 uint32_t x_lo;
95 uint32_t x_hi;
96 uint32_t y_lo;
97 uint32_t y_hi;
98 uint32_t z_1;
99 uint32_t z_2;
101};
102
103// Embedded curve point addition/subtraction: (x1, y1) ± (x2, y2) = (x3, y3)
105 uint32_t x1;
106 uint32_t y1;
107 uint32_t x2;
108 uint32_t y2;
109 uint32_t x3;
110 uint32_t y3;
111 bool is_addition; // else, subtraction
112};
113
114// Embedded curve point doubling: 2 * (x1, y1) = (x3, y3)
115template <typename FF> struct ecc_dbl_gate_ {
116 uint32_t x1;
117 uint32_t y1;
118 uint32_t x3;
119 uint32_t y3;
120};
121
122// Databus lookup gate: reads value at index from kernel_calldata/returndata
123template <typename FF> struct databus_lookup_gate_ {
124 uint32_t index;
125 uint32_t value;
126};
127
128// External gate data for poseidon2 external round
129template <typename FF> struct poseidon2_external_gate_ {
130 uint32_t a;
131 uint32_t b;
132 uint32_t c;
133 uint32_t d;
134 size_t round_idx;
135};
136
137// Initial linear layer gate for Poseidon2. Wires hold the raw permutation input; the next row
138// holds M_E * input and is consumed by the first external-round gate.
139template <typename FF> struct poseidon2_initial_external_gate_ {
140 uint32_t a;
141 uint32_t b;
142 uint32_t c;
143 uint32_t d;
144};
145
146// Internal gate data for poseidon2 internal round
147template <typename FF> struct poseidon2_internal_gate_ {
148 uint32_t a;
149 uint32_t b;
150 uint32_t c;
151 uint32_t d;
152 size_t round_idx;
153};
154
155// K=4 compressed internal-round gate: processes FOUR consecutive internal rounds per row.
156// Wires: a = state[0] at round 4i+0, b = state[0] at round 4i+1,
157// c = state[0] at round 4i+2, d = state[0] at round 4i+3.
158// (s_1, s_2, s_3) at row start are reconstructed inside the relation via a 3x3 Vandermonde solve.
159//
160// Round constants on the row (see Poseidon2QuadInternalRelationImpl):
161// q_l, q_r, q_o, q_4 = c_{4i}, c_{4i+1}, c_{4i+2}, c_{4i+3} // this quad's 4 S-box constants
162// q_m, q_c, q_5 = c_{4(i+1)}, c_{4(i+1)+1}, c_{4(i+1)+2} // next quad's first 3 constants
163// // (unused on terminal row)
164template <typename FF> struct poseidon2_quad_internal_gate_ {
165 uint32_t a; // state[0] at round 4i+0
166 uint32_t b; // state[0] at round 4i+1
167 uint32_t c; // state[0] at round 4i+2
168 uint32_t d; // state[0] at round 4i+3
169 size_t round_idx_start; // absolute round_constants index of round 4i (this quad's 1st round)
170 size_t next_pair_start; // absolute round_constants index of round 4(i+1) (next quad's 1st round);
171 // ignored when is_terminal = true
172 bool is_terminal; // true on the last compressed row (successor is standard-encoded)
173};
174
175// Entry transition gate: standard-encoded state (s_0, s_1, s_2, s_3) at round `round_idx_start`
176// whose successor is the first K=4 compressed row. The relation forces the successor's
177// w_r_shift, w_o_shift, w_4_shift to state[0] at rounds start+1, start+2, start+3 respectively.
178//
179// Round constants on the row:
180// q_l, q_r, q_o = c_{start}, c_{start+1}, c_{start+2} (first 3 internal round constants)
181// q_4, q_m, q_c, q_5 = 0 (unused)
182template <typename FF> struct poseidon2_transition_entry_gate_ {
183 uint32_t a; // s_0
184 uint32_t b; // s_1
185 uint32_t c; // s_2
186 uint32_t d; // s_3
187 size_t round_idx_start; // absolute round_constants index of the first internal round
188};
189} // namespace bb
Entry point for Barretenberg command-line interface.
Definition api.hpp:5
BilinearBatchedEqMode
Definition gate_data.hpp:58
bb::VectorAffineElementPushSpan< BaseParams > lhs
bb::VectorAffineElementPushSpan< BaseParams > rhs
friend bool operator==(arithmetic_triple_< FF > const &lhs, arithmetic_triple_< FF > const &rhs)=default
BilinearBatchedEqMode mode
Definition gate_data.hpp:61
uint32_t d
uint32_t a
uint32_t c
uint32_t b
size_t round_idx_start